Boundary scan testing of integrated circuits is typically used to identify faulty connections, such as unconnected or shorted pins. Boundary scan tests allow designers to quickly identify manufacturing or layout problems, which could otherwise be nearly impossible to isolate, especially with high-count ball-grid array packages. In a typically testing scenario, test equipment or software is used to generate test vectors, which are then delivered to a boundary scan chain in the integrated circuit. The boundary scan chain includes various storage elements connected in a chain throughout the device. Output of the boundary scan chain is then monitored and compared to expected results. Exemplary boundary scan devices include, application specific integrated circuits (ASICs) and programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).
A well-known boundary scan architecture is described in IEEE standard 1149.1, which is commonly known as JTAG (Joint Test Action Group). JTAG-compliant devices have dedicated hardware that includes a state machine and several storage elements (e.g., flip-flops or registers). This dedicated hardware interprets instructions and data provided by four dedicated signals. These signals are defined by the JTAG standard to be: test data in (TDI), test data out (TDO), test mode select (TMS), and test clock (TCK). The dedicated JTAG hardware interprets instructions and data on the TDI and TMS signals, and drives data out on the TDO signal. The TCK signal is used to clock the process.
Manufacturers of boundary scan devices typically provide a boundary scan description, which details the specific boundary scan architecture of the device. For example, manufacturers of a JTAG-compliant device provide a boundary scan description language (BSDL) file for that device. The BSDL file includes information on the function of each of the pins on the device (e.g., which pins are used as I/Os, which are power or ground, and the like), as well as the structure of the boundary scan chain. BSDL is a subset of VHDL (Very High Speed Integrated Circuit Hardware Description Language). One portion of a BSDL file describes the boundary scan chain within the device.
One previous methodology for generating a BSDL file for a device used a fully annotated schematic of the device having numerous tags that identify critical features related to the boundary scan architecture. The tags allowed for a process to extract the necessary information with respect to the boundary scan architecture from the annotated schematic in order to produce a BSDL file. The tags for the annotated schematic are typically added manually and are thus prone to error. Accordingly, there exists a need in the art for an improved method and apparatus for generating a boundary scan description and model for an integrated circuit.